<div class="entry-content">
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 <div class="blog-content">
 In this video we will design our own CPU. Explained by Steve Hoover
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 <div class="blog-content-chapters">
 <div>
 Chapters:
 </div>
 <ul class="chapters-list">
 <li class="chapters-list-item">00:00What this video is about</li>
 <li class="chapters-list-item">00:39Generating a CPU core</li>
 <li class="chapters-list-item">02:09Inside of CPU and how it works</li>
 <li class="chapters-list-item">05:58What are registers</li>
 <li class="chapters-list-item">07:38Program counter (PC)</li>
 <li class="chapters-list-item">11:16How a program is executed in CPU</li>
 <li class="chapters-list-item">17:19Logic gates explained</li>
 <li class="chapters-list-item">30:34Building our own CPU</li>
 <li class="chapters-list-item">39:37Instruction described - what is in it</li>
 <li class="chapters-list-item">40:52OPCODE</li>
 <li class="chapters-list-item">1:17:44If you would like to learn more</li>
 <li class="chapters-list-item">1:18:48Uploading our design to FPGA</li>
 </ul>
 </div>
 <div class="blog-content-links">
 <div>
 Links:
 </div>
 <ul class="links-list">
 <li class="links-list-item"><a href="https://makerchip.com">RMakerchip</a></li>
 <li class="links-list-item"><a href="https://redwoodeda.com">Redwood EDA</a></li>
 <li class="links-list-item"><a href="https://makerchip.com/sandbox/?tabs=Courses">RISC-V Courses (in Makerchip)</a></li>
 <li class="links-list-item"><a href="https://www.youtube.com/channel/UCskxhptNNMVyqi6LfCgwz9A">Redwood EDA YouTube</a></li>
 <li class="links-list-item"><a href="https://www.linkedin.com/in/steve-hoover-a44b607/">Steve Hoover’s Linkedin</a></li>
 <li class="links-list-item"><a href="https://fedevel.com/courses">FEDEVEL courses</a></li>
 </ul>
 </div> 
</div>

How Does a CPU Work and How To Create Your Own Processor

After this course, you will know how to:
<ul>
<li>Design digital logic</li>
<li>Implement a basic pipelined CPU core</li>
<li>Work with the base (RV32I) RISC-V instruction set</li>
<li>Use the online Makerchip development environment</li>
</ul>

What will you learn?

This course is for hobbyists, students, professors, and professionals at all levels. It is for anyone with a technical mindset, an interest in semiconductors and digital logic, and a desire to stay current with modern technology.

Who is this course for?

This course is a highly hands-on experience in digital circuit design and CPU microarchitecture. After a series of learning exercises, the course focuses on implementing a RISC-V CPU Core.

Lectures and lab activities cover:

<ul>
<li>Logic Gates</li>
<li>Combinational Logic</li>
<li>Makerchip Platform</li>
<li>Sequential Logic</li>
<li>Pipelined Logic</li>
<li>TL-Verilog Syntax and Constructs</li>
<li>A Calculator Circuit with Various Modifications</li>
<li>Clock Gating</li>
<li>RISC-V CPU Core Microarchitecture</li>
<li>Instruction Fetch Logic</li>
<li>Instruction Decode Logic</li>
<li>Arithmetic Logic Unit</li>
<li>Register File</li>
<li>Branch/Jump Logic</li>
<li>Pipelined CPU</li>
<li>Control Hazards</li>
<li>Data Hazards</li>
<li>Waterfall Diagrams</li>
<li>Register Bypass/Forwarding</li>
<li>PC Redirects</li>
<li>Data Memory, Loads and Stores</li>
</ul>

Description

Certification Instructions 
Certification requirements begin as soon as you start work on your CPU core. 

To receive certification for this course: 
After each lesson (after starting your CPU), upload your CPU source code at that point in the course. We need to see your incremental progress.
At the end of the course, also upload a reflection of your experience in this course. Reflect on the technologies you learned about and the skills you acquired. We want to hear how your experience impacts your career and personal growth. One paragraph will suffice, but we love to hear more. 

GitHub 
GitHub is the new resume. In addition to showing off your certificate, display what you have done in an online repository like GitHub. It's perfectly fine to share your work publicly. We like that. If you are new to Git/GitHub, this will be a great excuse to learn about these essential tools. 

You can create and update your repository through the online GitHub interface, or you can work in a local clone of your repository and commit/push your changes using git commands. (Note that Makerchip supports local file editing in Chrome and Edge.) 

Be sure to create an attractive README for your repository. Make it personal. Describe your motivation and learning journey. Reflect on the skills you acquired and the technologies you learned. Highlight the significance of your accomplishments. Include screenshots, and even put together an animated .gif. This is how you catch the eye of a prospective employer. The course reflection you submit can simply be a link to this repository/README.

Certificate

Price

This course is hands-on with numerous labs. Lab time will vary by individual. Generally, the course requires 20-30 focused hours of work. This includes about 4 hours of lectures distributed over 10 lessons, and the remaining time is for lab assignments.

Duration

Requirements

Even with no circuit design experience, you can create your own pipelined RISC-V core.

Learn to design digital logic for ASICs and FPGAs using next-generation Verilog (Transaction-Level Verilog) design in the online Makerchip IDE. In just a week, you can build and simulate a pipelined RISC-V CPU core from your browser. After this course, you will understand digital logic design concepts and advanced design methods. You'll become familiar with the RISC-V instruction set architecture, and you'll understand how a CPU executes RISC-V instructions to run a computer program.This course is appropriate for newcomers to digital logic and experts alike. Industry veterans will refresh their toolbox with a fresh perspective on familiar concepts, learning an approach to logic design that has not been possible until recently.

With no circuit design experience, you can create your own pipelined RISC-V core.

Building your own RISC-V Processor

Logic Gates; Combinational Logic; Makerchip Platform; Sequential Logic; Pipelined Logic; TL-Verilog Syntax and Constructs; A Calculator Circuit with Various Modifications; Clock Gating; RISC-V CPU Core Microarchitecture; Instruction Fetch Logic; Instruction Decode Logic; Arithmetic Logic Unit; Register File; Branch/Jump Logic; Pipelined CPU; Control Hazards; Data Hazards; Waterfall Diagrams; Register Bypass/Forwarding; PC Redirects; Data Memory, Loads and Stores

<ul>
<li>Intro to Logic Gates</li>
<li>Basic MUX Implementation and Intro to Makerchip</li>
<li>Labs for Combinational Logic</li>
</ul>

Length: 34:26

Introduction to digital logic, logic gates, and combinational logic. Introduction to the Makerchip online development environment. Labs include a calculator circuit.

Combinational Logic

Digital Logic

<ul>
<li>Intro to Sequential Logic and Counter Lab</li>
<li>Sequential Calculator Lab</li>
</ul>

Length: 14:31

Introduction to sequential logic. Labs include a counter and modifying the calculator to sequence calculations.

Sequential Logic

<ul>
<li>Pipelined Logic and Retiming</li>
<li>Pipelined Logic Advantages and Demo in Makerchip</li>
<li>Pipeline Coding and Labs</li>
<li>What to Do When You are Stuck</li>
<li>Reference Solutions with Visualization (link provided)</li>
<li>Starting-Point Code and Lab (link provided)</li>
<li>Lab on 2-Cycle Calculator</li>
</ul>

Length: 36:13

Pipelining logic for high performance. Labs include pipelining the calculator circuit.

Pipelined Logic

<ul>
<li>Intro to Validity and its Advantages</li>
<li>Demo of Total Distance Logic with When Condition</li>
<li>Demo of Total Distance Logic with When Condition (cont'd)</li>
<li>Lab on Calculator with Validity</li>
<li>Lab on Calculator with Single-Value Memory</li>
</ul>

Length: 33:55

Modeling the validity of computations and its benefits for error checking, debugging, and reducing power with fine-grained clock gating. Modeling state that holds its value by default. Labs include adding validity (and therefore clock gating) as well as adding a single-value memory to the calculator circuit.

Validity (When Conditions)

Modeling Validity of Signals and State

<ul>
<li>Microarchitecture of Single-Cycle RISC-V CPU</li>
<li>Starting-point Code for RISC-V Labs</li>
<li>Reference Solutions Showing Visualization and Things to Come</li>
</ul>

Length: 17:39

A typical microarchitecture of a single-cycle RISC-V CPU core. Overview of the CPU lab environment.

RISC-V CPU Preparation

Basic CPU Microarchitecture

<ul>
<li>Implementation Plan and Lab for PC</li>
<li>Lab for Instruction Fetch Logic</li>
<li>Lab for RISC-V Instruction Types (IRSBJU) Decode</li>
<li>Lab for Instruction Immediate Decode Logic</li>
<li>Lab to Decode Instruction Fields</li>
<li>Lab to Apply 'When' Condition to Instruction Fields</li>
<li>Lab to Decode Individual Instructions</li>
</ul>

Length: 19:58

Concepts and lab exercises for developing logic to maintain the program counter (PC), fetch instructions, and decode instructions.

Instruction Fetch and Decode

Instruction Fetching and Decoding

<ul>
<li>Lab for Register File Read</li>
<li>Lab fol ALU Operations for ADD, ADDI</li>
<li>Lab for Register File Write</li>
<li>Concept of Array and Register File Details</li>
<li>Lab for Implementing Branch Instructions</li>
<li>Lab for Completing Branch Instruction Implementation</li>
<li>Lab to Create Simple Testbench</li>
</ul>

Length: 22:43

Concepts and lab exercises for instantiating the register file for reading instruction operands and writing instruction results, performing computations for arithmetic instructions in the arithmetic logic unit (ALU), and executing branch instructions that modify the program counter.

Register File, ALU, and Branching

<ul>
<li>Introduction to Control and Data Flow Hazards</li>
<li>Lab to Create 3-Cycle Valid Signal</li>
<li>Lab to Update CPU to Execute Every Third Cycle</li>
<li>Lab to Distribute Logic Over Three Pipeline Stages</li>
</ul>

Length: 20:03

Control flow hazards and data flow hazards in pipelined CPUs. Labs for pipelining the CPU core in a three-cycle pipeline with simple low-performance assumptions.

Simple Pipelining, Executing an Instruction Every Three Cycles

Simple Pipelining of the CPU

<ul>
<li>Lab to Address Data Hazards with Register File Bypass/Forwarding</li>
<li>Lab to Address Control Flow Hazards (for Branches)</li>
<li>Lab to Complete Instruction Decode</li>
<li>Lab to Code Complete ALU</li>
</ul>

Length: 15:22

Lab exercises that address hazards, including register forwarding/bypass logic. Completing instruction decode and ALU logic for a baseline (RV32I) RISC-V CPU core.

Control and Data Hazard Logic

Improving Performance

<ul>
<li>Intro to Load/Store Instructions and Lab for Load Redirect</li>
<li>Lab to Load Data from Memory to Register File</li>
<li>Lab to Instantiate Data Memory</li>
<li>Lab to Add Stores and Loads to the Test Program</li>
<li>Lab to Add Control Logic for Jump Instructions</li>
<li>Wrap-up</li>
</ul>

Length: 31:56

Introduction to data memory operations. Labs to instantiate a data memory, load data from memory to registers, store data from registers to memory, and test memory instructions. Lab to add control logic for jump instructions. Course wrap-up.

Data Memory and Load and Store Instructions

Data Memory, Loads, and Stores, and Jumps

Includes: Online video access for 12 weeks (can be extended by 1 month for FREE) All lessons available immediately1 certificate (if you complete activities) 100% money-back guarantee up to 30 days from order

Online

Includes: Online access to this course for up to 3 people, each access for 12 weeks Every online access can be extended 2 times for FREE, each time for 1 more month ALL lessons accessible immediately after payment Unlimited video access (after downloaded) Video download available (after 30 days) Certificate for up to 3 people (when they complete activities) 100% money-back guarantee up to 30 days from order

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Includes: Online access to this course for up to 5 people, each access for 12 weeks Every online access can be extended 3 times for FREE, each time for 1 more month ALL lessons accessible immediately after payment Unlimited video access (after downloaded) Video download available immediately after payment Certificate for up to 5 people (when they complete activities) 100% money-back guarantee up to 30 days from order

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With nearly 20 years of experience developing CPU and network chips for high-performance computing systems and several years as founder and CEO of Redwood EDA, Steve Hoover brings a great deal of industry knowledge to his courses.Steve holds a BS in electrical engineering from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He contributed to multiple generations of Alpha microprocessors at DEC and Compaq as well as Itanium and Xeon server projects and Omni-Path HPC network switch microarchitecture for Intel. Recognizing the urgency for a new design paradigm, Steve left Intel to found Redwood EDA in 2015. He is fostering an open-source hardware ecosystem with the introduction of makerchip.com, and he is actively contributing to the evolution of the Transaction-Level Verilog standard.

Steve Hoover

With nearly 20 years of experience developing CPU and network chips for high-performance computing systems and several years as founder and CEO of Redwood EDA, Steve Hoover brings a great deal of industry knowledge to his courses.

With over 20 years of experience in the electronics industry, Robert Feranec is a distinguished engineer who has contributed to numerous high-profile projects. His diverse roles include hardware designer at VOIPAC Technologies and senior hardware engineer at EUROTECH.Robert is known for his expertise in the field of hardware design, particularly in the areas of PCB design, signal integrity, and high-speed digital design. In addition to his role as a founder and CEO of FEDEVEL, he is a passionate content creator on YouTube. There, he provides valuable tips, tricks, and tutorials on PCB design and electronics engineering. Robert's commitment to education and innovation continues to inspire and empower the next generation of electronics engineers.

Robert Feranec

With over 20 years of experience in the electronics industry, Robert Feranec is a distinguished engineer who has contributed to numerous high-profile projects. His diverse roles include hardware designer at VOIPAC Technologies and senior hardware engineer at EUROTECH.

With a diverse skill set, Philip's areas of specialization span from high-speed, mixed-signal electronics for industrial drones to cutting-edge audio electronics. He is also a sought-after industrial consultant and content creator for Altium. Philip holds a degree in Electronics and Control Systems Engineering from the University of Cambridge, England, and is certified by IPC CID+, demonstrating his expertise in the industry.His identity is greatly shaped by his renowned YouTube channel, Phil's Lab. As an experienced hardware and PCB design consultant, Philip uses his channel as a platform to share educational engineering content, covering topics such as PCB design, electronics, and real-time digital signal processing.

Philip Salmony

With a diverse skill set, Philip's areas of specialization span from high-speed, mixed-signal electronics for industrial drones to cutting-edge audio electronics.He is also a sought-after industrial consultant and content creator for Altium. Philip holds a degree in Electronics and Control Systems Engineering from the University of Cambridge, England, and is certified by IPC CID+, demonstrating his expertise in the industry..

Steven is a power system engineering veteran with over 40 years of experience. As a globally acclaimed authority, Steve frequently lectures and conducts workshops on Power Integrity and Distributed Power System Design. He has been awarded the DesignCon 2017 and EDICON 2017 Best Paper Awards, and was a winner of the Jim Williams ACE Award for Contributor of the Year (2015), as well as DesignCon 2023 Engineer of the Year award. Steve is also a two-time Test & Measurement Test Engineer of the Year Finalist.With numerous publications and books on power supply and distribution network performance, including his latest book "Power Integrity Using ADS" (2020), Steve is a leading authority in the field. Additionally, he is the founder of AEi Systems, specializing in modeling and worst-case circuit analysis for high reliability industries. He is also the founder and CEO of PICOTEST.com, which is a company specializing in instruments and accessories for high-performance power systems and distributed system testing.

Steve Sandler

Steven is a power system engineering veteran with over 40 years of experience. As a globally acclaimed authority, Steve frequently lectures and conducts workshops on Power Integrity and Distributed Power System Design. He has been awarded the DesignCon 2017 and EDICON 2017 Best Paper Awards, and was a winner of the Jim Williams ACE Award for Contributor of the Year (2015), as well as DesignCon 2023 Engineer of the Year award. Steve is also a two-time Test & Measurement Test Engineer of the Year Finalist.

The founder and principal EMC consultant, who brings extensive expertise in power electronics, digital electronics, electric machines, and product design. With a PhD from Newcastle University's Electrical & Electronics Engineering department, where his research focused on novel power switching schemes to reduce EMI emissions, Min's work has been widely cited in research papers. He has worked as an EMC specialist on milestone projects with Dyson Technology in the UK, establishing EMC capabilities for the Dyson Electric Vehicle project.Following that, he joined Cherry Clough Consultants Ltd to provide independent expertise in cost-effective EMC design worldwide. Now he works as a principal EMC consultant in Mach One Design Ltd. Dr. Min Zhang's in-depth knowledge and proven track record in designing cutting-edge electronics and electric machines with minimal EMC issues make him a valuable asset in helping you achieve efficient and cost-effective product designs.

Min Zhang

The founder and principal EMC consultant, who brings extensive expertise in power electronics, digital electronics, electric machines, and product design. With a PhD from Newcastle University's Electrical & Electronics Engineering department, where his research focused on novel power switching schemes to reduce EMI emissions, Min's work has been widely cited in research papers. He has worked as an EMC specialist on milestone projects with Dyson Technology in the UK, establishing EMC capabilities for the Dyson Electric Vehicle project.

Keith has dedicated his career to solving real-life interference problems in high-tech products and systems across various industries. Graduating with a B.Sc (Hons.) in Electrical Engineering from Imperial College London in 1972, he specialized in analogue circuit design and electromagnetic field theory, earning Upper Second Class Honours (Cum Laude).Throughout his career, he has managed critical projects, such as developing a new range of microwave test instruments (the 6200 series) for Marconi Instruments. As a Chartered Electrical Engineer since 1978 and a Group 1 European Engineer since 1988, Keith has authored numerous papers on EMC and EMC for Functional Safety. He has also held leadership roles in professional organizations, including chairing the IEE's Professional Group (E2) on Electromagnetic Compatibility and the IEE's Working Group on 'EMC and Functional Safety', and serving as the UK expert for the IEC 61000-1-2 maintenance team.

Keith Armstrong

Years in Electronic Design and Management

EMC Specialist & Chartered Electrical Engineer

Keith has dedicated his career to solving real-life interference problems in high-tech products and systems across various industries. Graduating with a B.Sc (Hons.) in Electrical Engineering from Imperial College London in 1972, he specialized in analogue circuit design and electromagnetic field theory, earning Upper Second Class Honours (Cum Laude).

With a decade of hands-on experience in Altium Designer and Altium Enterprise Systems, this engineering expert is passionate about training professionals to maximize their proficiency and efficiency using these powerful tools. Gaining extensive knowledge through his work as a hardware developer at IDS-Imaging Development Systems GmbH, Sven has managed the transition to Altium Designer, implemented Altium Vault and Altium Concord Pro, and overseen PLM integration.Over the years, he has continued to broaden, extend, and deepen his expertise through numerous development projects. Sven is the founder of the company EDATRON Solutions GmbH (link→ <a href='https://www.edatron-solutions.com/en' style='color: white; text-decoration: underline;'>https://www.edatron-solutions.com/en</a>), where he currently leads practical Altium training sessions. These sessions take place both at the customer's location and at a training center in Germany. As a skilled trainer, Sven has successfully supported several customers in implementing Altium's enterprise products, as well as consulting about Altiums software solutions.

Sven Ingelfinger

With a decade of hands-on experience in Altium Designer and Altium Enterprise Systems, this engineering expert is passionate about training professionals to maximize their proficiency and efficiency using these powerful tools. Gaining extensive knowledge through his work as a hardware developer at IDS-Imaging Development Systems GmbH, Sven has managed the transition to Altium Designer, implemented Altium Vault and Altium Concord Pro, and overseen PLM integration..

A talented FPGA engineer with degrees in Electronic and Computer Engineering Technology and Electrical Engineering from the University of Dayton, Jordan also has a patent pending for an innovative electronic monitoring device. Proficient in FPGA development, digital electronics, circuit board design, and VHDL design and modeling of hardware systems, his expertise is rooted in embedded systems.His passion for engineering extends beyond academia, as he actively pursues diverse interests that allow him to further develop his skills. These include mobile application development, PCB layout and assembly, computer application programming, and various other electrical engineering pursuits, demonstrating his commitment to continuous learning and innovation in the field.

Jordan Christman

A talented FPGA  engineer with degrees in Electronic and Computer Engineering Technology and Electrical Engineering from the University of Dayton, Jordan also has a patent pending for an innovative electronic monitoring device. Proficient in FPGA development, digital electronics, circuit board design, and VHDL design and modeling of hardware systems, his expertise is rooted in embedded systems.

Sierra Circuits excels in providing high-quality, quick-turn PCBs and medium production runs, prioritizing rapid delivery and unmatched product quality. Committed to offering customers exceptional resources and knowledge, their industry-leading circuit boards are designed to withstand even the most extreme conditions.One striking example of their product resilience is a cubesat board that not only survived a catastrophic rocket explosion but also remained undamaged after plummeting back to earth. It is important to emphasize that their cubesat board was not the cause of the explosion. Sierra Circuits' steadfast dedication to engineering and innovation ensures their position at the forefront of the industry, meeting and exceeding customer expectations.

Sierra Circuits

Sierra Circuits excels in providing high-quality, quick-turn PCBs and medium production runs, prioritizing rapid delivery and unmatched product quality. Committed to offering customers exceptional resources and knowledge, their industry-leading circuit boards are designed to withstand even the most extreme conditions.

XJTAG specializes in enabling engineers to swiftly debug, test, and program complex electronic circuit boards, streamlining design, development, and manufacturing processes. With a focus on innovative product development and high-quality technical support, the company caters to a diverse array of industries, including aerospace, automotive, defense, medical, manufacturing, networking, and telecommunications.XJTAG's global presence is supported by an extensive network of over 50 experienced distributors and technology partners, ensuring clients worldwide can access their products and services. By delivering exceptional solutions that facilitate efficient electronic circuit board management, XJTAG helps industries optimize their operations and achieve greater success.

XJTAG

XJTAG specializes in enabling engineers to swiftly debug, test, and program complex electronic circuit boards, streamlining design, development, and manufacturing processes. With a focus on innovative product development and high-quality technical support, the company caters to a diverse array of industries, including aerospace, automotive, defense, medical, manufacturing, networking, and telecommunications.

Voipac provides scalable and compact COMs and SBCs, covering all of the technologically and development demanding parts, significantly cutting customers’ new products time-to-market.Since 2002, Voipac team has served numerous satisfied customers from all over the world. Its focus is to maintain close links with not only other commercial companies, but also with the technical institutes and university students that will once graduate and become the driving force of the future development teams.

Voipac

New product development projects realized

Institutes and universities using our SBCs and COMs

Years of learning and experiences gathering

Voipac provides scalable and compact COMs and SBCs, covering all of the technologically and development demanding parts, significantly cutting customers’ new products time-to-market.

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