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everdrone , 07-25-2025, 07:15 PM

It's my first BGA project. All other examples of MCUs have the SDRAM interface grouped on one edge or corner of the BGA, but the STM32H7 has data, address and control pins scattered across the grid. This makes the layout difficult (can't pick the best position and orientation of the two chips). I am trying to use a 6 layer stackup (3 routing layers) or an 8 layer stackup at most. Only TH vias.
Do you have a reference of a similar design? Are there application notes on how to route memory on STM32s with this ballout?
Thanks in advance

QDrives , 07-26-2025, 01:32 PM

Are there no alternative pin options?

everdrone , 07-26-2025, 06:29 PM

Only for SNDE and SDCKE and a few others. The address and data buses are not interchangeable at all

Robert Feranec , 07-28-2025, 11:34 AM

how they do in in reference design?

QDrives , 07-28-2025, 07:05 PM

If I recall correctly, there is a discovery board that also has SDRAM.

everdrone , 07-28-2025, 10:16 PM

I'm using MB1381 as reference, the other design with SDRAM uses a lot more devices on the same lines and it's less similar to what I have to do (super long SDRAM traces).
MB1381 in the attached pics (L1, L4, L6 respectively) uses a different BGA for the sdram that allows more space between traces I think, should I switch to the 90-TFBGA?

everdrone , 07-28-2025, 10:16 PM

everdrone , 07-28-2025, 10:17 PM

Where I'm at right now

everdrone , 07-28-2025, 10:19 PM

The reference design looks beautiful and professional, mine looks amateur 😭
I still need to untangle the lines where the series termination resistors are, I feel like that's the problematic location now

QDrives , 07-28-2025, 11:18 PM

"*The reference design looks beautiful and professional...*" -- I do not know which I looked at currently, but I was not impressed by the two Nucleo I looked at.

QDrives , 07-28-2025, 11:20 PM

What pitch did you select?
How much space do you have?
The biggest pitch I know of is 0.8mm.

everdrone , 07-29-2025, 12:52 AM

Everything is evenly distributed, every trace has it’s way without weird turns, look optimally. No idea how else to put it tbh. Both stm32 and sdram are 0.8mm currently. I will try to rotate the sdram around and see how the traces come out during preliminary routing. This orientation seems to produce very short and long traces in the same group (9mm and 62mm)

everdrone , 07-29-2025, 12:53 AM

The ST application note for the H7 specifies that the address command and control lines should stay within a 20mm margin of each other, while there should be a 10mm margin in relation to the clock signal

everdrone , 07-29-2025, 12:55 AM

Also, should I add a serpentine to the clock? The application note advises against it but there’s no way to keep the margin below 10mm with such a short clock line

everdrone , 07-29-2025, 01:18 AM

All the space I want, I’m trying to keep it compact to save it as a reuse block

everdrone , 07-29-2025, 01:33 AM

This is the ideal

QDrives , 07-29-2025, 01:34 AM

There you can see the part numbers and orientation.

everdrone , 07-29-2025, 10:04 AM

Ok i checked and it seems that the x16 configuration is not available in BGA packages with > 54 balls, so the package for the memory is the same.
That design looks very dense, I don't think they're using any termination resistors unless they crammed them all on the bottom layer, which is unlikely

everdrone , 07-30-2025, 10:12 AM

For reference, this is one layer of a 4-layer board where only the top and bottom are routed. This is how good the layout could've looked if ST placed the FMC pins according to standards and not by rolling a dice