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Forum / Schematic Design & PCB Layout / Delay matching requirement for Clock Enable (CKE) signal on DDR3

Delay matching requirement for Clock Enable (CKE) signal on DDR3

sam , 08-06-2025, 01:27 AM

Hello,

I am finishing up my high speed digital board design but I realized that I missed out clock enable signal as part of delay matching requirement for DDR3 routing. I am doing fly-by routing using two DDR3 memories with Zynq7010 series. Please see attached for my schematic, routing that shows xSignal nets and Zynq application note (UG933). According to this app note, It dosen't look like that I need match delays on clock enable signals but only controlled impeadnce but I wasn't too clear about it. Can anyone confirm about this? I am aware that I don't need delay matching for NRST (reset) signal but needed a clarification on clock enable. App note specifically mentions about Data group and Address, Command, Control trace length requirement and they define data group and addr,cmd,ctrl signal as below,

Data : dq, dqs, dm (for each group)
Address : Addr, we_b, ras_b, cas_b, odt, cs_b

Thank you!