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Joel R. , 06-30-2026, 04:00 AM

Hello, I’m new to Altium Designer, so I hope someone can help me.

When I place a via, a large green area appears around it, and I’m not sure what it represents or which layer it belongs to. I tried hiding the layers one by one, but it does not seem to correspond to any visible layer. I also tried adjusting some design rules, but I’m still quite lost.

Could someone please explain what this green area is and how I can control its size? It looks a little too large for my design. I’m uploading images showing the issue in both 2D and 3D mode.
Thank you.

, 06-30-2026, 04:03 AM

🤖 In the meantime, here’s a response from the [FEDEVEL AI HW Assistant]().
It helps to find relevant resources for your question, but it may make mistakes as it’s still in early development.

This is the response from the AI Assistant:
The green areas around vias in Altium Designer indicate **design rule violations**, specifically clearance issues between the via and other copper objects (like polygons or tracks). This is controlled by your **Clearance Constraint Rules** and **Polygon Connect Style Rules**. Here's how to address it:

1. **Main Culprit: Polygon Clearance**
- The green halo appears when your via violates the minimum clearance distance from copper pours (polygons). This is especially common with ground/power planes.
- Adjust the **Polygon Clearance Rule** in *Design > Rules > Electrical > Clearance*:
```plaintext
First Object: IsVia
Second Object: IsRegion (for polygons)
Set your required clearance (typical values: 0.1-0.2mm)
```
[Example of adjusting polygon-via clearance rules](https://www.youtube.com/watch?v=w9gxB6XVHnk&t=1555)

2. **Via Tent Settings**
- If using tented vias (solder mask covering via), check your **Solder Mask Expansion** rule:
```plaintext
Design > Rules > Manufacturing > Solder Mask Expansion
```
- Large expansions can create oversized mask openings that might appear as green areas if conflicting with other mask features.

3.

, 06-30-2026, 04:03 AM

**Quick Check Method**
- Press `T > D > R` to run Design Rule Check
- Double-click the green violation marker to see exact rule being violated
- Use `Tools > Design Rule Check` to modify rules directly from violation reports

**Pro Tip:** For dense designs, create specific rules for vias near BGAs or tight spaces:
```plaintext
New Clearance Rule > Query: InComponent('U1')
Set smaller clearance for components needing tighter via spacing
```
[Example of component-specific clearance rules](https://www.youtube.com/watch?v=B8wQVrPKTSw&t=148)

The green areas will disappear once your via spacing complies with the rules. Start with 0.15mm clearance as default, then tighten where needed.

You can continue chatting with the AI Assistant here:
https://fedevel.com/hw-assistant

Joel R. , 06-30-2026, 04:14 AM

I don’t think it is a Design Rule violation because when I pressed T > D > R, around 500 rule violations were detected, but none of them concerned vias. All of them were related to unrouted signals. I'll keep looking into it.

Robert Feranec , 06-30-2026, 05:07 AM

its the area around via without copper on power plane. Do you have power planes in your stackup? have a look at them. Power planes are negative - means the places with color are the places without copper.

Joel R. , 07-01-2026, 03:32 AM

Thank you for the clue. It turns out it was related to the Power Plane Clearance. I reduced it to 0.254 mm, and the green area became smaller.
Do you happen to have a video about setting up rules in Altium Designer, Mr. Feranec?

Thank you again.