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Miro , 11-08-2023, 09:42 AM

Hello,
Is there a rule or other way to avoid the following situation, where the width is too small but plane is not broken:

Robert Feranec , 11-08-2023, 11:34 AM

is this between layers?

Miro , 11-08-2023, 12:38 PM

Yes, this is a power plane. In this particular case - it is between GND plane layer and signal layer

QDrives , 11-08-2023, 04:33 PM

What width is to small? It looks like you are showing the "width" of the gnd plane below and next to the signal.
Are you referring to the return path rule?

Miro , 11-09-2023, 07:23 AM

This is a printscreen from internal power plane (negative). Between the arrows, very thin copper exists this means that the power rail (split plane) is not broken but I want to avoid such a narrow places.

Miro , 11-09-2023, 07:26 AM

Minimum Copper Width in Power plane (Split plane)

Miro , 11-09-2023, 07:27 AM

Minimum Copper Width in Internal Negative Power plane (Split plane)

Miro , 11-09-2023, 07:33 AM

I can't find a way to post a new picture...

Miro , 11-09-2023, 07:33 AM

found it :)😆

Robert Feranec , 11-09-2023, 07:52 AM

now I know what you mean - I am not sure if this is possible on power plane. that is one of the reasons why I rather use polygons for power layers - there you can set minimum width

Miro , 11-09-2023, 07:59 AM

Thanks Robert! My colleagues do the same (using polygons) ... I always check this manually but this needs a lot of time and the results are not always what expected to be 😆 like the above situation which is real and found after manufacturing the boards.

chill7 , 11-12-2023, 03:48 PM

Using a Power Analyzer would show narrow areas... also current density and DC drop.