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Dead copper DRC error

samuelalbu , 11-01-2023, 08:29 PM
I always seem to get this error. I have checked thorughly if vias are connected to GND net repectively polygon is connected to GND. All looks good, but the error is still there.
QDrives , 11-01-2023, 09:04 PM
My guess is that on layer L1 there is some unconnected (dead) copper.
You have to make that layer visible before you can see the issue. Double clicking on the message does not do that for you.
samuelalbu , 11-02-2023, 01:17 PM
I found it finally 🙂 It only occured to me now that I might have copied two vias with the polygon above for Q2. Those two vias connect POK1 and POK2 over 200k pullup to +5V_VCC. They are both placed next to Q2 MOSFET, so Q1 did not need those vias. They were connecting to the +5V_VCC signal layer 4 but was not needed since they don't distribute that net to any pin of the SMPS controller, not any other component.
samuelalbu , 11-02-2023, 01:20 PM
today with a bit of clear mind I had a look over Robert's design (1st image) and it occured to me. Second image in my design shows the issue. Sometimes it is good also to use the All Layers view and select each layer one by one, when I reached GND layer it was clear to me. Also it is good to let silk screen on to not have to always use cross probe and see where it connects. Gives an indea a bit faster of what could be wrong and where.
QDrives , 11-02-2023, 09:57 PM
The amount of times you have to change the view configuration while doing the layout is immense -- at least if you want to keep a clear/clean view.
samuelalbu , 11-03-2023, 03:31 PM
I still can't figure the dead copper error. I have looked everywhere, i see no dead copper in that area.
Robert Feranec , 11-03-2023, 05:47 PM
delete all copper on L1 have a look if the problem is still there, then Undo, delete half of the board an check if that fixed the problem, continue until you find out what exactly is causing the problem.
QDrives , 11-04-2023, 01:13 AM
@Robert Feranec I hope never to use those extreme measures!
But for @samuelalbu select layer L1, go to single layer mode (shift-S) until only that layer is visible. Now select the violation and optionally zoom out.
You might see some thin lines for the border of a polygon pour.
Another possibility is that you did not check the box of "remove islands less than" and/or "remove dead copper" of a polygon on that layer.
Robert Feranec , 11-04-2023, 06:02 AM
@QDrives it can always be done on a copy of the project, no damage if something goes wrong. it's very fast way to locate problems
QDrives , 11-04-2023, 02:55 PM
I did something like that once on a project that did not zoom correctly. When I did View / Fit document (Ctrl-PgDn), it would zoom out way more than the content.
Made a copy and started deleting thing to find out what it is. When I had deleted everything, it was still not zooming correctly.
What else could it be....
In the end, it turns out that it may have been violations that remained and they are cleared (cleaned) with Design / Netlist / Clean all nets.
I had spend many hours trying to find out how to solve this.
Recently had a similar issue with the design of an intern. Same solution.
samuelalbu , 11-05-2023, 05:04 PM
@Robert Feranec Thanks for your feedback. I already did that. Still no dead copper to be seen. Even connected those two vias to the GND pads.
samuelalbu , 11-05-2023, 05:07 PM
@QDrives Thanks for the suggestions. I did use always shift+S, zoom out did not show anything. But "remove dead copper" seems I did not check the box in the Preferences panel. Re run DRC but the error is still there.
samuelalbu , 11-05-2023, 05:21 PM
@QDrives Tried Design - Netlist - Clean all Nets, also nothing has changed after running DRC. I made sure each time to recomplile (cc) the project.
samuelalbu , 11-05-2023, 05:23 PM
But all very good inputs @QDrives and @Robert Feranec. Thanks! I will still try to figure this out. Spent hours on this. Left this for a couple of days as it is, hoped I come back with clear mind.
samuelalbu , 11-05-2023, 05:34 PM
with Health Check I might find something...
samuelalbu , 11-05-2023, 05:45 PM
https://tenor.com/view/ive-made-it-william-easton-saw6-i-did-it-ive-finished-it-gif-21986627
samuelalbu , 11-05-2023, 05:45 PM
WOW! this seems to have worked. I am so so happy. hahaha 😅 this has taken quite some hours of my life this week. I wanted to finish the board and move on the generating the output files, I could have even waive this error and manufactured this board. But who knows me personally knows that I suffer from OCD, and this thing here really triggered my old self, glad this is over. Let's see what challenges I will face with other boards.
samuelalbu , 11-05-2023, 05:50 PM
Actually I made it thanks to all the very helpful inputs you guys had given me, @QDrives & @Robert Feranec It has taken me step by step into the right direction. Found this actually in my desperation today, saw quite a few times, the Health Check tab, I guessed it wouldn't hurt checking what the button does. 😬
QDrives , 11-05-2023, 08:07 PM
What do you have layer L1? It should either be a plane or have a (single) polygon pour connected to Gnd.
However, the violation states that it does not have a net associated with it.
Select layer L1, single layer mode (no other layers visible) and press Ctrl-A. What shows now as being selected? You might press Del key to delete it.
(optional) Tools / polygon pours / Restore x shelved polygons
Tools / polygon pours / Repours all
Now do the design rule check.
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