Home / Tag Archives: Cadence Allegro

Tag Archives: Cadence Allegro

Review of Server PCB Layout & Schematic – Part 7: MISC

server board part 7

This video is about: Layer ordering, Poured GND on signal layers, 90 Degree angles, Power plane pulled back, Fiducials, USB & Ethernet shield, Non hierarchical schematic Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files – Olympus Intel: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download

Read More »

Review of Server PCB Layout & Schematic – Part 6: DDR4 Memory Layout & CPU Power

server board part 6

This video is about: DDR4 Layout, DDR4 Power Planes, Tabbed Routing, 90A (MAX 255A) Power Supply Planes, CPU Decoupling, Non PCB Components Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files – Olympus Intel: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download

Read More »

Review of Server PCB Layout & Schematic – Part 5: SFP 10Gb/s Interface

sfp layout

This video is about: SFP Layout, Backdrilled VIAs, PSU Connector, Impedance Coupons, OCuLink, SMBus Switch, I2C to UART Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files – Olympus Intel: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download

Read More »

Review of Server PCB Layout & Schematic – Part 4: PCI Express (PCIE)

zig zag

This video is about: Zig-Zag routing, Stitching VIAs, Stub in PINs, Holes in GND under PADS and around VIAs, Port 80 & POST Codes Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files – Olympus Intel: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download Cadence document: https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/pcb-design-analysis/pcb-west-2016-new-techniques-address-layout-challenges-high-speed-routing-cp.pdf 100Gbps design guidlines document: https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an684.pdf

Read More »

Review of Server PCB Layout & Schematic – Part 3: Baseboard Management Controller (BMC)

part 3 picture

This video is about: DDR3, VGA, BMC Decoupling, Power monitoring, BIOS Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download

Read More »

Review of Server PCB Layout & Schematic – Part 2: Platform Controller Hub (PCH)

Server board part 2 green

This video is about: SATA, USB 3.0, PCH Decoupling, Differential Pairs and Length Compensation, Info in Schematic, Level Translators, SPD Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download

Read More »

Review of Server PCB Layout & Schematic – Part 1: Processor

server board part 1 v3

This video is about: Server Board Project Olympus, Block Diagrams, Processor Schematic & DDR4 Memory slots, PCB Layout around CPU Project Olympus: https://www.opencompute.org/wiki/Server/ProjectOlympus Files: http://files.opencompute.org/oc/public.php?service=files&t=e969672c57d6e17647adea54f2c3e5a7&download

Read More »

How To Do DDR3 Memory PCB Layout Simulation – Step by Step Tutorial

simulation screenshot

After watching this video you will have the most important info which will help you to simulate your own PCB layout. We will be using Cadence Sigrity, SystemSI, SPEED2000 and Allegro. iMX6 Rex project: http://www.imx6rex.com/ Github with files: https://github.com/FEDEVEL/board-imx6rex-module-in-cadence Would you like to support me in what I do? It’s …

Read More »