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  • Layer based length matching

    Hello Robert,

    I am designing PCB with imX6 controller with 4 DDR3 chips same like your tutorial video & it is finding very useful to me.

    I have 2 questions:

    1. How important is to match the length by layerwise? I mean, for example, few of the lines in DATABYTE 1 are routed in Internal layer 4. So whatever the segment of the lines routed on that share must be same in length? Ofcourse total length in every group (Data, Address, Control etc.) from source pin to destination pin should me matched, no doubt about it.

    2. How important to route all the signals in each group in any specific layer only? For exa. - D0 to D7 shalled be routed in only one internal layer only, and no splitting of the lines (Like D0 to D4 in internal layer 1 & D5 to D7 in Internal layer 2. Is it allowed?

    I have 2 external layer & 2 intenal layers only so I am finding difficult to meet these requirnment. Please advise.

    Regards,
    Prasad K
    (India)



  • #2
    1) you have to match length wise only layer wise is not needed because the material stays the same.. Tpd is the same for all internal layers..
    2) it is important to at least try and do it. but in your case please add layers!! you also need power planes in there..

    keep in mind that its not only D0-D7 you also MUST match DM and DQS in that same group!

    it might seem that is more expensive to design it on 6 or 8 layers.. but the time you gain in the beginning of your project makes up for that 10 fold.

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    • #3
      Thanks Paul for reply & clarification.
      Sorry, I missed to mentioned that -I have only 4 'ROUTING ' layers only- 2 External & 2 Internal. I do have 4 GND planes & 2 Powers planes. (Total 10 layer stackup)

      Could you please share length report of your design (V1I1 imx6 )?

      (And, Yes, I am considering DM & DQS ofcourse. just not mentioned in the example. )

      Thanks again,
      Prasad Kulkarni
      Last edited by ppk1982; 03-20-2019, 05:35 AM.

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      • #4
        I would like to add:
        1) Simply to say, signal travels different speed on TOP and BOTTOM comparing to travelling in the middle (if you would like to know more have a look at my server video here: https://www.fedevel.com/welldoneblog...out-cpu-power/ ). For DDR3, I am not very strict in this topic, so I do not do any special legth matching on individual layers for DDR3 signals, but I am careful and I go into the internal layers as soon as it is possible.
        2) I always route the signals within datagroup same way

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