FPGA/SoC Board Bring-Up - DDR3 (Zynq Part 2) - Phil's Lab #97
How to configure and test DDR3 memory on custom Zynq-based hardware. Showing hardware set-up, fly-by routing strategy, Vivado and Vitis configuration, as well as memory area and eye diagram tests.
Chapters:
- 00:00Introduction
- 01:40Previous Video
- 02:25DDR3 Hardware Design Overview
- 06:19Vivado DDR3 Configuration (Datasheet)
- 13:15Vivado Training/Board Details (PCB Delays)
- 17:46Export Hardware (XSA)
- 18:24Vitis DRAM Test Set-Up
- 19:52Hardware Connection
- 20:08Memory Address Space Test
- 22:26Eye Diagram Tests
- 24:29Summary & What´s Next
- 25:22Outro
