DDR3 mirroring is a feature of memory controller.

See the following text from DDR3 SDRAM Unbuffered DIMM Design Specification (JEDEC website – Registration is required, page 17).

Following pins are being mirrored: A3<->A4, A5<->A6, A7<->A8, BA0<->BA1.

“Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a “load mode” operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.”

To confirm this, have a look on the following pictures from PC3-12800 UDIMM layout where I have selected A8 signal:

Details of A8 Top and Bottom Layer:

Screenshot from schematic for D1 and D9:

Components D1 and D9 are listed in the BOM with same part number.

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