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DDR3 memory mirroring – PCB layout

DDR3 mirroring is a feature of memory controller.

See the following text from DDR3 SDRAM Unbuffered DIMM Design Specification (JEDEC website – Registration is required, page 17).

Following pins are being mirrored: A3<->A4, A5<->A6, A7<->A8, BA0<->BA1.

“Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limitations however. When writing to the internal registers with a “load mode” operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring the address when accessing the second rank.”

To confirm this, have a look on the following pictures from PC3-12800 UDIMM layout where I have selected A8 signal:

Details of A8 Top and Bottom Layer:

Screenshot from schematic for D1 and D9:

Components D1 and D9 are listed in the BOM with same part number.

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  • http://www.edaboard.com/thread215207.html#post913660 DDR3 IC’s In a VERY Small PCB

    [...] [...]

  • http://www.alliance-express.com/circuit-board-hardware circuit board hardware

    Hello..
    I was looking for the circuit board facts as I have to complete my project on it and reached here. I am glad I visited here and gathered so much resource. One should always take care while working on it.

  • http://www.fedevel.com Robert Feranec

    thank you

  • Michael Kuzminov

    Hi Robert

    Firstly thank you very much that you share this information with us.

    I have a question about the data bus. Typically the memory chips are connected to the processor DQ[0..7] — DQ[0..7], DQ[0..7] — DQ[8..15], …, and so on, depending on the width of the data bus of the processor and the amount of memory chips used. It also can be seen in the specification on page 18-23.

    Why is the “Screenshot from schematic for D1 and D9″ they are connected on another, I’d seen on the electronic circuits from the manufacturer such a connection, and I thought it was wrong. Or where you can read about it.

    Thanks.

  • http://www.fedevel.com Robert Feranec
  • Michael Kuzminov

    Thanks

    I read the paragraph “3.5.1 Swapping data lines”
    Guide is cool
    :)

  • http://www.fedevel.com Robert Feranec

    :)

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