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Double DDR3 Routing

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  • #46
    Is this time difference too much or the DDR3 can handle this difference? MT41K512M16HA-107 :A
    Rogelio Basically, I do not use propagation delay to do length matching for couple of reasons. Some time ago I answered similar question here: http://www.fedevel.com/designhelp/fo...dr3-lpddr-ddr3

    I would like to have your comments about my procedure to length match the segments.
    - This video may help you: Altium – How to use xSignals ( in Fly-By, T-Branch + Other useful things )
    - Also, have a look at our OpenRex design (download the Altium files). Check how we did the layout there. It may be very similar to what you are doing, just OpenRex uses 4 memories: http://www.imx6rex.com/open-rex/

    by the way what do you use to simulate the signal behavior?
    If needed, I would recommend Hyperlinx - they have a nice wizard for memory simulation.

    I also know which are the best practices, but engineering bought an evaluation board which was routed in 6 layers.
    I think, the most critical part will be fanout of the BGA and how many power planes you will need. If you have enough space and if the BGA pins are ordered for an easy fanout, it may be possible to use 6 layers, however normally it is not the case

    T-S-S-G-P-P-G-S-S-B
    Maybe this can help: 3 STEPS How to determine / calculate number of PCB layers

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    • #47
      Hi dear Robert. my DDR2 controller can not support ODT pin in DDR2 memories, in the controler's datasheet writen: "On-die Termination" and connect to ground. but, I am goin to connect to VDD=1.8V directly for enable ODT. and useing it's
      Is there any problem? could you help me please?

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      • #48
        If you are not sure, provide both options: pull up + pull down resistor and test the board. You can then decide ....

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        • #49
          Ok, But I don't want use those resistors because the compaction of my board will be high, if it be possible, I do not use from they.
          ODT pin is a pin that , for enable or disable ( On or Off) and internal resistor's selector is a two bit in address bus (i read in micron datasheet A2 & A6).
          For enable of ODT pin I want use a IO pin from controller. A common pin or normal IO pin. what do you think??????

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          • #50
            Good morning Robert,
            I was able to separate Address from control I routed both on internals, but seems I'll need to do the same but using 2 different internal layers to pass over the Address for the Data and data control lines,
            I'm going to need 3 or 4 layers for HS signals, will be enough to use a 10 layer PCB? or shoud I go to 12?

            Top sig
            GND
            HS
            HS
            GND
            PWR mixed
            HS ( full plane under HS sig) with coupling caps to GND near vias
            HS
            GND
            Bott sig

            this does not look too good for the layer near PWR but I might manage to have an unbroken section under it.

            So
            for 12

            Top
            GND
            HS
            HS
            GND
            PWR 3.3
            PWR mixed
            GND
            HS
            HS
            GND
            Bott sig

            Do you have a better stack order?
            Its complicated to go out of the uP in the same layer with the whole bunch for address or Data.
            Thanks for your help

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            • #51
              Arash yahyapour It's really up to you Be sure, you can control the IO pin before you activate the memory, be sure it has correct initial (after reset) level. Also, you only need two resistors to support the pull up / down option.

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            • #52
              Rogelio some time ago I wrote a post which you can find on Altium blog. Have a look it can help you: How to Route DDR3 Memory and CPU fan-out

              Also have a look at our reference designs, how we routed the individual groups. You can download Altium files of our open source projects from: http://www.imx6rex.com/

              PS: What are the tracks routed on the last picture? Are this ADDR/CMD/CTL or they include also DATA tracks?

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              • #53
                I grouped ADD0 to 15 and CLK, and on the other layer BA, RAS, CKE CS,CAS, WE, ODT, RESET. Should I move the CLK with the control signals, I haven't grouped the data signals yet, I'm trying to figure it out how to.
                I just downloaded the example, I'll check it, thanks.

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                • #54
                  Rogelio you can group and route ADDR & CMD separately, that is fine. CLK is a group itself. Have a look for example on iMX6 Design guide (google for "iMX6 Design guide"). That may help you with groups and routing: http://cache.nxp.com/assets/document...6DQ6SDLHDG.pdf

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                  • #55
                    Hi dear Robert
                    in simulation I have AC overshoot and undershoot in driver pins (SAM9g45) (between 160mv to 300mv) and I was try to resolve their by change in value of series resistor. but I can not success. Of course, signals have been received in memory pins don't have any AC over/undershoot .is it normal? if No, how can I resolve their?
                    do you see how different between reading signal and writing signal, If I adjust the resistors for writing,...so reading signal will be fail.and if I adjust the resistors for reading,...so writing signal will be fail. it is funny. could you help me please. Thank you.
                    Attached Files
                    Last edited by Arash yahyapour; 01-14-2017, 10:00 AM.

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                    • #56
                      Signal depends on many factors, not just series termination resistors e.g. external termination, internal termination of memories and memory controller, routing topology, placement, layout, ..... Very often you will get different results for Read and Write. If you need to simulate memory interface, try Hyperlynx memory wizard, that may help you (it also tells you if your layout pass or fail).

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                      • #57
                        Hi dear Robert I think my layout about DDR2 with 133MHz finished. I simulated it's with Hyperlynx single signal one by one. the signals of DQX and DQS and Address and commands were good. I checked with eye diagram and they were nice signals. after that I did "Run DDRx Batch simulation" and set all of parameters carefully. after run, the result simulation been fail, status was fail. I searched the problem and find that, problem is in initializing of driver " SAM9G45_TFBGA324". the massage of error is :
                        "** Error **: Missing driver model; unable to simulate;
                        ** Info **: Initialization of drivers failed!"
                        I did assign model of driver. it is " IBIS Signal: sam9g45_tfbga324.ibs "
                        could you help me please . what is my problem.
                        the best regards.

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                        • #58
                          Do you have IBIS models for your DDR as well? It is a bit difficult to troubleshoot such problems from a distance.

                          Comment


                          • Arash yahyapour
                            Arash yahyapour commented
                            Editing a comment
                            Yes, I have . it means , it is default file in software and during to assign model, I found it and define, but my problem is in side of driver,
                            and the software didn't has IBIS model for driver in it's library. I searched in Atmel site and downloaded it's.
                            Last edited by Arash yahyapour; 02-03-2017, 01:19 AM.

                        • #59
                          The best would be maybe if you talk to your Hyperlynx support. I do not own the software, I only can use it occasionally when some of my clients have it. Also as mairomaster explained, it's not so simple and it takes some time to simulate designs - that is the reason why we do not do it for every board - we only simulate when we have to break too many rules.

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                          • #60
                            Hi dear Robert my design is finished. I want to make it. we have a large variety of board. so I can not select their.1- which one is suitable for my design?? I sow your stack up parameters. 2- for example: VT47-106 VT47-1080 VT47 what different between their??
                            3- you written in your table about "impedance" . for example: target impedance= 90 calculated impedance= 90.060
                            - how to find your target impedance??
                            - how to calculate that ​impedance??
                            please kindly to answer me
                            the best regards

                            Comment

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