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  • CPU-Power distribution

    Hello Team,

    I am trying to understand the layout of lesson 5 for memory module. i was trying to understand the placement of decoupling capacitor.

    As shown in attachment, i was not able to find the source for net (+1V2_VDD_ARM_CAP).
    all I found is the decoupling capacitor and power plane in layer 7. i am not able to address, where this supply (+1V2_VDD_ARM_CAP) is generated.

    Regards
    Meet Payak

  • #2
    This is a very special power. If you have a look inside CPU datasheet, you will find there information about internal regulator. There is no external power source for this net.

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    • #3
      Thanks a lot Ferance for your reply... keep helping to learn the world of High speed design...

      Regards
      Meet

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      • #4
        Hello Robert,
        I am doing lesson 2 with expert option. i m confused to place big value capacitor 22uF, where to place them .. 220nF i was successful to place, but not sure for 22uF. please refer the attachment.
        can you please suggest for placement please.
        Also i am curious to know, how far we can place small value capacitor or their is priority for signal and relaxed for others.

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        • #5
          If you are not sure, the best way is to have a look at reference designs. You can download Altium projects of our http://www.imx6rex.com/ boards and have a a look at decoupling under BGA.

          Basically, you would like to keep the capacitors with smallest values as close as possible to the pins. The bigger caps can be a little bit further - somewhere on the way to the smaller caps.

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