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  • CPU-Power distribution

    Hello Team,

    I am trying to understand the layout of lesson 5 for memory module. i was trying to understand the placement of decoupling capacitor.

    As shown in attachment, i was not able to find the source for net (+1V2_VDD_ARM_CAP).
    all I found is the decoupling capacitor and power plane in layer 7. i am not able to address, where this supply (+1V2_VDD_ARM_CAP) is generated.

    Regards
    Meet Payak

  • #2
    This is a very special power. If you have a look inside CPU datasheet, you will find there information about internal regulator. There is no external power source for this net.

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    • #3
      Thanks a lot Ferance for your reply... keep helping to learn the world of High speed design...

      Regards
      Meet

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